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Vol. 1, Issue 2, 2004April 01, 2004 EDT

Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package

Xiaowu Zhang, E. H. Wong, Mahadevan K. Iyer,
Wafer Level Chip Scale PackageSolder Joint ReliabilityThermal FatigueFinite Element ModelCreep Analysis
Copyright Logoccby-nc-nd-4.0 • https://doi.org/10.4071/1551-4897-1.2.64
Journal of Microelectronics & Elect Pkg
Zhang, Xiaowu, E. H. Wong, and Mahadevan K. Iyer. 2004. “Board Level Reliability Enhancement for A Double-Bump Wafer Level Chip Scale Package.” Journal of Microelectronics and Electronic Packaging 1 (2): 64–71. https:/​/​doi.org/​10.4071/​1551-4897-1.2.64.
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