ISSN 1551-4897
Vol. 1, Issue 2, 2004April 01, 2004 EDT
Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package
Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package
Zhang, Xiaowu, E. H. Wong, and Mahadevan K. Iyer. 2004. “Board Level Reliability Enhancement for A Double-Bump Wafer Level Chip Scale Package.” Journal of Microelectronics and Electronic Packaging 1 (2): 64–71. https://doi.org/10.4071/1551-4897-1.2.64.