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Vol. 12, Issue 4, 2015
October 01, 2015 EDT
Process Optimization for 3-D IC Assembly
Charles G. Woychik
,
Sangil Lee
,
Scott McGrath
,
Sitaram Arkalgud
,
2.5-D
3-D IC
TSV
microbumped die
Si interposer
CTE
warpage
JEDEC reliability specifications
chip stacking
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ccby-nc-nd-4.0
•
https://doi.org/10.4071/imaps.474
Journal of Microelectronics & Elect Pkg
Woychik, Charles G., Sangil Lee, Scott McGrath, and Sitaram Arkalgud. 2015. “Process Optimization for 3-D IC Assembly.”
Journal of Microelectronics and Electronic Packaging
12 (4): 219–25.
https://doi.org/10.4071/imaps.474
.
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