ISSN 1551-4897
Vol. 8, Issue 4, 2011October 01, 2011 EDT
An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration
An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration
Articles in Vol. 8, Issue 4, 2011
Vol. 8, Issue 4, 2011
- Assessment and Characterization of Stress Induced by Via-First TSV TechnologyG. ParèsF. De CrecyS. MoreauC. MauriceA. BorbelyJ. MazuirL.L. ChapelonN. Sillon
- An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC IntegrationShyh-Shyuan SheuZhe-Hui LinJui-Feng HungJohn H. LauPeng-Shu ChenShih-Hsien WuKeng-Li SuChih-Sheng LinShinn-Juh LaiKuo-Hsing ChengTzu-Kun KuWei-Chung LoMing-Jer Kao
- A Comparison of Back Grinding Processes for Bare Silicon and Through-Silicon Via Wafers Using Numerical SimulationsA. H. AbdelnabyG. P. PotirnicheA. ElshabiniF. BarlowR. Parker
- Planar Double-Sided Anode Supported SOFC—Novel DesignBarbara DziurdziaZbigniew Magonski
- Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)J. H. LauC.-J. ZhanP.-J. TzengC.-K. LeeM.-J. DaiH.-C. ChienY.-L. ChaoW. LiS.-T. WuJ.-F. HungR.-M. TainC.-H. LinY.-C. HsinC.-C. ChenS.-C. ChenC.-Y. WuJ.-C. ChenC.-H. ChienC.-W. ChiangH.-H. ChangW.-L. TsaiR.-S. ChengS.-Y. HuangY.-M. LinT.-C. ChangC.-D. KoT.-H. ChenS.-S. SheuS.-H. WuY.-H. ChenW.-C. LoT.-K. KuM.-J. KaoD.-C. Hu
- System-on-Chip Integrated MEMS Packages for RF LNA Testing and Self-CalibrationBruce C. KimSukeshwar KannanSai Shravan EvanaSeok-Ho Noh
Sheu, Shyh-Shyuan, Zhe-Hui Lin, Jui-Feng Hung, John H. Lau, Peng-Shu Chen, Shih-Hsien Wu, Keng-Li Su, et al. 2011. “An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration.” Journal of Microelectronics and Electronic Packaging 8 (4): 140–45. https://doi.org/10.4071/imaps.307.