Vol. 8, Issue 4, 2011October 01, 2011 EDT
A Comparison of Back Grinding Processes for Bare Silicon and Through-Silicon Via Wafers Using Numerical Simulations
A Comparison of Back Grinding Processes for Bare Silicon and Through-Silicon Via Wafers Using Numerical Simulations
Abdelnaby, A. H., G. P. Potirniche, A. Elshabini, F. Barlow, and R. Parker. 2011. “A Comparison of Back Grinding Processes for Bare Silicon and Through-Silicon Via Wafers Using Numerical Simulations.” Journal of Microelectronics and Electronic Packaging 8 (4): 146–53. https://doi.org/10.4071/imaps.298.