ISSN 1551-4897
Vol. 9, Issue 1, 2012January 01, 2012 EDT
Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration
Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration
Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng, John H. Lau, Yi-Feng Hsu, Jui-Chin Chen, Yu-Chen Hsin, Chien-Chou Chen, Shang-Hung Shen, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao,
Articles in Vol. 9, Issue 1, 2012
Vol. 9, Issue 1, 2012
- Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill TechnologyJonathan TamilSiew Hoon OreKian Yeow GanDrake KohMichael Gantalao Ti InBoon Pek LiewTeck Wah ParkGeraldine NgYong Bo YangDaniel TehNathapong SuthiwongsunthornSurasit Chungpaiboonpatana
- Reflection Phase Shift for PWB and PCBA Production TestingAbdelghani RenbiJerker Delsing
- Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC IntegrationChien-Ying WuShang-Chun ChenPei-Jer TzengJohn H. LauYi-Feng HsuJui-Chin ChenYu-Chen HsinChien-Chou ChenShang-Hung ShenCha-Hsin LinTzu-Kun KuMing-Jer Kao
- Quantitative Assessment of the Effects of Strain on Future III-V Digital ApplicationsUmesh P. GomesKumud RanjanSubhra ChowdhuryPalash DasServin RathiDhrubes Biswas
- Design and Characterization of a Biocompatible Packaging Concept for Implantable Electronic DevicesMaaike Op de BeeckKaren QianPaolo FioriniKarl MalachowskiChris Van Hoof
- Use of Wafer Applied Underfill for 3D StackingAntonio La MannaK. J. RebibisC. GeretsE. Beyne
Wu, Chien-Ying, Shang-Chun Chen, Pei-Jer Tzeng, John H. Lau, Yi-Feng Hsu, Jui-Chin Chen, Yu-Chen Hsin, et al. 2012. “Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 Mm Wafers for 3D IC Integration.” Journal of Microelectronics and Electronic Packaging 9 (1): 31–36. https://doi.org/10.4071/imaps.308.