ISSN 1551-4897
Vol. 9, Issue 1, 2012January 01, 2012 EDT
Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration
Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration
Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng, John H. Lau, Yi-Feng Hsu, Jui-Chin Chen, Yu-Chen Hsin, Chien-Chou Chen, Shang-Hung Shen, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao,
Wu, Chien-Ying, Shang-Chun Chen, Pei-Jer Tzeng, John H. Lau, Yi-Feng Hsu, Jui-Chin Chen, Yu-Chen Hsin, et al. 2012. “Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 Mm Wafers for 3D IC Integration.” Journal of Microelectronics and Electronic Packaging 9 (1): 31–36. https://doi.org/10.4071/imaps.308.