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Vol. 9, Issue 1, 2012January 01, 2012 EDT

Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology

Jonathan Tamil, Siew Hoon Ore, Kian Yeow Gan, Drake Koh, Michael Gantalao Ti In, Boon Pek Liew, Teck Wah Park, Geraldine Ng, Yong Bo Yang, Daniel Teh, Nathapong Suthiwongsunthorn, Surasit Chungpaiboonpatana,
flip chipMUFsimulationvoid
Copyright Logoccby-nc-nd-4.0 • https://doi.org/10.4071/imaps.319
Journal of Microelectronics & Elect Pkg
Tamil, Jonathan, Siew Hoon Ore, Kian Yeow Gan, Drake Koh, Michael Gantalao Ti In, Boon Pek Liew, Teck Wah Park, et al. 2012. “Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology.” Journal of Microelectronics and Electronic Packaging 9 (1): 19–30. https:/​/​doi.org/​10.4071/​imaps.319.
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