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Vol. 9, Issue 1, 2012
January 01, 2012 EDT
Use of Wafer Applied Underfill for 3D Stacking
Antonio La Manna
,
K. J. Rebibis
,
C. Gerets
,
E. Beyne
,
3D Integration
multi-die stacking
wafer applied underfill
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ccby-nc-nd-4.0
•
https://doi.org/10.4071/imaps.317
Journal of Microelectronics & Elect Pkg
La Manna, Antonio, K. J. Rebibis, C. Gerets, and E. Beyne. 2012. “Use of Wafer Applied Underfill for 3D Stacking.”
Journal of Microelectronics and Electronic Packaging
9 (1): 10–18.
https://doi.org/10.4071/imaps.317
.
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