Vol. 8, Issue 4, 2011October 01, 2011 EDT
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)
J. H. Lau, C.-J. Zhan, P.-J. Tzeng, C.-K. Lee, M.-J. Dai, H.-C. Chien, Y.-L. Chao, W. Li, S.-T. Wu, J.-F. Hung, R.-M. Tain, C.-H. Lin, Y.-C. Hsin, C.-C. Chen, S.-C. Chen, C.-Y. Wu, J.-C. Chen, C.-H. Chien, C.-W. Chiang, H.-H. Chang, W.-L. Tsai, R.-S. Cheng, S.-Y. Huang, Y.-M. Lin, T.-C. Chang, C.-D. Ko, T.-H. Chen, S.-S. Sheu, S.-H. Wu, Y.-H. Chen, W.-C. Lo, T.-K. Ku, M.-J. Kao, D.-C. Hu,
Lau, J. H., C.-J. Zhan, P.-J. Tzeng, C.-K. Lee, M.-J. Dai, H.-C. Chien, Y.-L. Chao, et al. 2011. “Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 Mm Multi-Project Wafer (MPW).” Journal of Microelectronics and Electronic Packaging 8 (4): 171–78. https://doi.org/10.4071/imaps.306.