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Vol. 6, Issue 1, 2009January 01, 2009 EDT

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

Karan Kacker, Suresh K. Sitaraman,
wafer level packagingchip to substrate interconnectsfirst level interconnectscompliant interconnectsflip chip assembly
Copyright Logoccby-nc-nd-4.0 • https://doi.org/10.4071/1551-4897-6.1.59
Journal of Microelectronics & Elect Pkg
Kacker, Karan, and Suresh K. Sitaraman. 2009. “Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect.” Journal of Microelectronics and Electronic Packaging 6 (1): 59–65. https:/​/​doi.org/​10.4071/​1551-4897-6.1.59.
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