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Vol. 5, Issue 2, 2008April 01, 2008 EDT

Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP)

M. Khalil Abdullah, M.Z. Abdullah, M.A. Mujeebu, S. Kamaruddin, Z.M. Ariff,
Encapsulationsfinite difference method (FDM)die thicknessvoidflow retardation
Copyright Logoccby-nc-nd-4.0 • https://doi.org/10.4071/1551-4897-5.2.62
Journal of Microelectronics & Elect Pkg
Abdullah, M. Khalil, M.Z. Abdullah, M.A. Mujeebu, S. Kamaruddin, and Z.M. Ariff. 2008. “Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP).” Journal of Microelectronics and Electronic Packaging 5 (2): 62–67. https:/​/​doi.org/​10.4071/​1551-4897-5.2.62.
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