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Vol. 3, Issue 4, 2006
October 01, 2006 EDT
Methods for Reducing Power Loss in On-Wafer Inductors
Päivi H. Karjalainen
,
Pekka Heino
,
CMOS
inductor
integrated components
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ccby-nc-nd-4.0
•
https://doi.org/10.4071/1551-4897-3.4.194
Journal of Microelectronics & Elect Pkg
Karjalainen, Päivi H., and Pekka Heino. 2006. “Methods for Reducing Power Loss in On-Wafer Inductors.”
Journal of Microelectronics and Electronic Packaging
3 (4): 194–200.
https://doi.org/10.4071/1551-4897-3.4.194
.
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