ISSN 1551-4897
Vol. 17, Issue 4, 2020October 01, 2020 EDT
Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers
Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers
John H. Lau, Cheng-Ta Ko, Tzvy-Jang Tseng, Chia-Yu Peng, Kai-Ming Yang, Tim Xia, Puru Bruce Lin, Eagle Lin, Leo Chang, Hsing Ning Liu, Curry Lin, David Cheng, Winnie Lu,
Articles in Vol. 17, Issue 4, 2020
Vol. 17, Issue 4, 2020
- Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced WafersJohn H. LauCheng-Ta KoTzvy-Jang TsengChia-Yu PengKai-Ming YangTim XiaPuru Bruce LinEagle LinLeo ChangHsing Ning LiuCurry LinDavid ChengWinnie Lu
- Reliable Nickel-Free Surface Finish Solution for High-Frequency, HDI PCB ApplicationsKunal Shah
- Optimization of PCB SI Coupon Design That Minimizes Discontinuity Through via-in-Pad Plated over (VIPPO) TechniqueJuhee LeeKyeongsoo KimSimon KimKiseop KimKyungsoo Lee
Lau, John H., Cheng-Ta Ko, Tzvy-Jang Tseng, Chia-Yu Peng, Kai-Ming Yang, Tim Xia, Puru Bruce Lin, et al. 2020. “Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers.” Journal of Microelectronics and Electronic Packaging 17 (4): 111–20. https://doi.org/10.4071/imaps.1226533.