ISSN 1551-4897
Vol. 8, Issue 4, 2011October 01, 2011 EDT
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)
J. H. Lau, C.-J. Zhan, P.-J. Tzeng, C.-K. Lee, M.-J. Dai, H.-C. Chien, Y.-L. Chao, W. Li, S.-T. Wu, J.-F. Hung, R.-M. Tain, C.-H. Lin, Y.-C. Hsin, C.-C. Chen, S.-C. Chen, C.-Y. Wu, J.-C. Chen, C.-H. Chien, C.-W. Chiang, H.-H. Chang, W.-L. Tsai, R.-S. Cheng, S.-Y. Huang, Y.-M. Lin, T.-C. Chang, C.-D. Ko, T.-H. Chen, S.-S. Sheu, S.-H. Wu, Y.-H. Chen, W.-C. Lo, T.-K. Ku, M.-J. Kao, D.-C. Hu,
Articles in Vol. 8, Issue 4, 2011
Vol. 8, Issue 4, 2011
- Assessment and Characterization of Stress Induced by Via-First TSV TechnologyG. ParèsF. De CrecyS. MoreauC. MauriceA. BorbelyJ. MazuirL.L. ChapelonN. Sillon
- An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC IntegrationShyh-Shyuan SheuZhe-Hui LinJui-Feng HungJohn H. LauPeng-Shu ChenShih-Hsien WuKeng-Li SuChih-Sheng LinShinn-Juh LaiKuo-Hsing ChengTzu-Kun KuWei-Chung LoMing-Jer Kao
- A Comparison of Back Grinding Processes for Bare Silicon and Through-Silicon Via Wafers Using Numerical SimulationsA. H. AbdelnabyG. P. PotirnicheA. ElshabiniF. BarlowR. Parker
- Planar Double-Sided Anode Supported SOFC—Novel DesignBarbara DziurdziaZbigniew Magonski
- Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)J. H. LauC.-J. ZhanP.-J. TzengC.-K. LeeM.-J. DaiH.-C. ChienY.-L. ChaoW. LiS.-T. WuJ.-F. HungR.-M. TainC.-H. LinY.-C. HsinC.-C. ChenS.-C. ChenC.-Y. WuJ.-C. ChenC.-H. ChienC.-W. ChiangH.-H. ChangW.-L. TsaiR.-S. ChengS.-Y. HuangY.-M. LinT.-C. ChangC.-D. KoT.-H. ChenS.-S. SheuS.-H. WuY.-H. ChenW.-C. LoT.-K. KuM.-J. KaoD.-C. Hu
- System-on-Chip Integrated MEMS Packages for RF LNA Testing and Self-CalibrationBruce C. KimSukeshwar KannanSai Shravan EvanaSeok-Ho Noh
Lau, J. H., C.-J. Zhan, P.-J. Tzeng, C.-K. Lee, M.-J. Dai, H.-C. Chien, Y.-L. Chao, et al. 2011. “Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 Mm Multi-Project Wafer (MPW).” Journal of Microelectronics and Electronic Packaging 8 (4): 171–78. https://doi.org/10.4071/imaps.306.