ISSN 1551-4897
Vol. 2, Issue 3, 2005July 01, 2005 EDT
Board Level Power Cycling and Thermal Cycling Fatigue Reliability of Chip-scale Packages
Board Level Power Cycling and Thermal Cycling Fatigue Reliability of Chip-scale Packages
Articles in Vol. 2, Issue 3, 2005
Vol. 2, Issue 3, 2005
- Interfacial Stresses in a Tri-Material Assembly Subjected to Differential Temperatures in the Layers in Electronic PackagingD. SujanM. V. V. MurthyK. N. SeetharamuA. Y. Hassan
- Design of Drop Test Apparatus for Electronic PackagesChang-Lin YehYi-Shao Lai
- Board Level Power Cycling and Thermal Cycling Fatigue Reliability of Chip-scale PackagesTong Hong WangYi-Shao LaiChang-Chi Lee
- Pretreatment of Blind Via Holes before Ni/Au and Cu Plating Applied with Atmospheric Pressure Plasma JetYasushi SawadaKeiichi YamazakiNoriyuki TaguchiTetsuji Shibata
- Soldering Properties and Interfacial Microstructure of CSP Solder Joints with Lower Melting Lead-free SolderAtsushi YamaguchiYuhei YamashitaAkio FurusawaKazuto NishidaTakashi HojoYosuke SogoAyako MiwaAkio HiroseKojiro F. Kobayashi
- Study of Interfacial Delamination by Considering the Effect of Temperature and Moisture during Solder Reflow for QFN PackageFu-Mauh WongK.N Seetharamu
- Lead Free Die Mount Adhesive Using Silver Nanoparticles Applied To Power Discrete PackageYasunari UkitaKazuki TateyamaMasao SegawaYoshihiko TojoHideyuki GotohKatsuhisa Oosako
Wang, Tong Hong, Yi-Shao Lai, and Chang-Chi Lee. 2005. “Board Level Power Cycling and Thermal Cycling Fatigue Reliability of Chip-Scale Packages.” Journal of Microelectronics and Electronic Packaging 2 (3): 171–79. https://doi.org/10.4071/1551-4897-2.3.171.