ISSN 1551-4897
Vol. 5, Issue 2, 2008April 01, 2008 EDT
Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP)
Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP)
Articles in Vol. 5, Issue 2, 2008
Vol. 5, Issue 2, 2008
- Reliability Assessment: New Tools for the Next Generation of PackagesIsabelle BordBruno LevrierYannick DeshayesLaurent BéchouYves Ousten
- Maximum Attainable Deflections of Shape Memory Alloy-Layered MicrocantileverP. MajumderA. Bhattacharyya
- Numerical Optimization of Silicon Stacked Module for 3-D Packaging ApplicationsAkella G.K. ViswanathXiaowu ZhangY.Y. WangS.W. YoonNavas KhanVaidyanathan Kripesh
- Laser Sintering of Silver Nanomaterial on Polymer SubstratesAdeyl KhanNicholas RasmussenValery MarinovOrven F. Swenson
- Heatsink Mass Optimization Methodology for Desktop Microprocessor CoolingAli A. MerrikhMike EymanDavid B. WalshakTom DolbearSridhar Sundaram
- Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP)M. Khalil AbdullahM.Z. AbdullahM.A. MujeebuS. KamaruddinZ.M. Ariff
Abdullah, M. Khalil, M.Z. Abdullah, M.A. Mujeebu, S. Kamaruddin, and Z.M. Ariff. 2008. “Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP).” Journal of Microelectronics and Electronic Packaging 5 (2): 62–67. https://doi.org/10.4071/1551-4897-5.2.62.